View CXD2467AQ_5782858.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

digital signal driver/timing generator description the CXD2467AQ incorporates digital signal processor type rgb driver and timing generator functions onto a single ic. operation is possible with a system clock up to 135mhz (max.). this ic can process video signals in bands up to sxga standard, and can output the timing signals for driving various lcd panels such as sxga (lcx028) and xga (lcx017 and lcx023). features various picture quality adjustment functions such as user adjustment, white balance adjustment and gamma correction osd mix, black frame processing, mute and limiter functions drives various data projector lcd panels such as sxga (lcx028) and xga (lcx017 and lcx023) controls the sample-and-hold position of the cxa2112r sample-and-hold driver line inversion and field inversion signal generation supports ac drive of lcd panels during no signal applications lcd projectors and other video equipment structure silicon gate cmos ic absolute maximum ratings (v ss = 0v) supply voltage v dd v ss ?0.5 to +4.0 v input voltage v i vss ?0.5 to v dd + 0.5 v output voltage v o vss ?0.5 to v dd + 0.5 v storage temperature tstg ?5 to +125 ? recommended operating conditions supply voltage v dd 3.0 to 3.6 v operating temperature topr ?0 to +75 ? ?1 e99613a08 sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXD2467AQ 240 pin qfp (plastic) note) company names and product names, etc. contained in these materials are the trademarks or registered trademarks of the respective companies.
?2 CXD2467AQ block diagram parallel i/f dsd tg iract 8 2 3 r, g, b in r, g, b out clkout hret, oract, hst, hck1, hck2, dck1, dck1x, dck2, dck2x, enb, pcg, clp1, clp2, vst, vck, frp, blk, rgt, xrgt, dwn, hb, vb1, vb2, sha, shb, shc, shd, inv xclr direct clear irret, iract psave1 psave2 10 2 3 2 2 3 r, g, b osd 2 ym 2 ys pctl pclk pdat clk2 clk1p clk1n clk1c 10 clksel1 clkpol1 clksel2 hdin1 hdpol1 vdin1 vdpol1 clk4 hdin2 hdpol2 clk3p clk3n clk3c clksel3 clkpol2 clksel4 d q q d q q
3 CXD2467AQ pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 190 191 192 193 194 195 196 183 182 181 184 185 186 187 188 189 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 g2osd0 b2osd1 b2osd0 ym2 ys2 v dd v ss pctl pclk pdat9 pdat8 pdat7 pdat6 pdat5 pdat4 pdat3 pdat2 v dd v ss pdat1 pdat0 hdin1 vdin1 hdpol1 vdpol1 clk1p clk1n v ss clk1c v ss clk2 v ss 41 42 43 44 45 46 47 48 49 50 51 52 clk3n v dd v ss clk3c v ss clk4 clksel3 clksel4 clkpol2 irret hret v ss 53 54 55 56 57 58 59 xclr v dd v ss b2out0 b2out1 b2out2 b2out3 60 b2out4 clkout v ss clksel1 clksel2 clkpol1 hdin2 hdpol2 clk3p r1in1 r1in2 r1in3 r1in4 r1in5 v ss v dd r1in6 r1in7 psave2 psave1 test4 test3 test2 test1 oract iract v ss v dd inv shd shc shb sha clp2 clp1 prg frp xrgt rgt v ss hst dck2x dck2 dck1x dck1 v dd hck2 hck1 blk 135 136 137 138 139 140 enb v ss v dd vck vst dwn 134 hb 133 v ss 132 vb1 131 vb2 130 pcg 129 r1out9 v ss b1out4 b1out5 b1out6 b1out7 b1out8 v ss b1out9 g2out0 g2out1 g2out2 61 62 63 64 65 66 67 68 69 70 71 b2out5 b2out6 b2out7 b2out8 b2out9 v dd v ss b1out0 b1out1 b1out2 b1out3 v ss g2out3 g2out4 g2out5 g2out6 g2out7 v dd v ss g2out8 g2out9 g1out0 g1out1 g1out2 v ss g1out3 g1out4 g1out5 g1out6 g1out7 v ss g1out8 g1out9 r2out0 r2out1 r2out2 v ss r2out3 r2out4 r2out5 r2out6 r2out7 v dd v ss r2out8 r2out9 r1out0 r1out1 r1out2 r1osd0 r1osd1 b2in0 b2in1 b2in2 b2in3 b2in4 v ss b2in5 b2in6 b2in7 b1in0 b1in1 b1in2 b1in3 b1in4 b1in5 b1in6 b1in7 v ss v dd g2in0 g2in1 g2in2 g2in3 g2in4 g2in5 g2in6 g2in7 g1in0 g1in1 v ss g1in2 g1in3 g1in4 g1in5 g1in6 g1in7 r2in0 r2in1 r2in2 r2in3 v ss v dd r2in4 r2in5 r2in6 r2in7 r1in0 111 110 109 108 107 106 105 118 119 120 117 116 115 114 113 112 104 103 102 101 100 230 231 232 233 234 235 236 237 ys1 ym1 v ss v dd b1osd0 b1osd1 g1osd0 g1osd1 238 239 240 g2osd1 r2osd0 r2osd1 127 128 r1out8 v ss 126 v dd 125 r1out7 124 r1out6 123 r1out5 122 r1out4 121 r1out3
4 CXD2467AQ pin description pin no. symbol i/o description input pin processing for open status 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 g2osd0 b2osd1 b2osd0 ym2 ys2 v dd v ss pctl pclk pdat9 pdat8 pdat7 pdat6 pdat5 pdat4 pdat3 pdat2 v dd v ss pdat1 pdat0 hdin1 vdin1 hdpol1 vdpol1 clk1p clk1n v ss clk1c v ss clk2 v ss i i i i i i i i i i i i i i i i i i i i i i i i i osd green data input (port 2) osd blue data input (port 2) osd blue data input (port 2) osd ym input (port 2) osd ys input (port 2) power supply gnd parallel i/f control signal input parallel i/f clock input parallel i/f data input parallel i/f data input parallel i/f data input parallel i/f data input parallel i/f data input parallel i/f data input parallel i/f data input parallel i/f data input power supply gnd parallel i/f data input parallel i/f data input horizontal sync signal input-1 vertical sync signal input-1 hdin1 input polarity selection (high: positive polarity, low: negative polarity) vdin1 input polarity selection (high: positive polarity, low: negative polarity) clock input-1 (small-amplitude differential input, positive polarity) clock input-1 (small-amplitude differential input, negative polarity) gnd clock input-1 (cmos input) gnd 1/2 frequency-divided clock input-1 (cmos input) gnd l l h l l
5 CXD2467AQ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 clkout vss clksel1 clksel2 clkpol1 hdin2 hdpol2 clk3p clk3n v dd v ss clk3c v ss clk4 clksel3 clksel4 clkpol2 irret hret v ss xclr v dd v ss b2out0 b2out1 b2out2 b2out3 b2out4 b2out5 b2out6 b2out7 b2out8 b2out9 o i i i i i i i i i i i i o o i o o o o o o o o o o 1/2 frequency-divided clock output gnd input clock selection (high: clk1c, low: clk1p, n) input clock selection (high: clk2, low: clk1) 1/2 frequency division circuit output selection (high: xq output, low: q output) horizontal sync signal input-2 hdin2 input polarity selection (high: positive polarity, low: negative polarity) clock input-2 (small-amplitude differential input, positive polarity) clock input-2 (small-amplitude differential input, negative polarity) power supply gnd clock input-2 (cmos input) gnd 1/2 frequency-divided clock input-2 (cmos input) input clock selection (high: clk3c, low: clk3p, n) input clock selection (high: clk4, low: clk3) 1/2 frequency division circuit output selection (high: xq output, low: q output) auxiliary pulse output auxiliary pulse output gnd external clear (low: reset) power supply gnd blue data output (port 2) blue data output (port 2) blue data output (port 2) blue data output (port 2) blue data output (port 2) blue data output (port 2) blue data output (port 2) blue data output (port 2) blue data output (port 2) blue data output (port 2) l l l l l l l h pin no. symbol i/o description input pin processing for open status
6 CXD2467AQ 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 v dd vss b1out0 b1out1 b1out2 b1out3 v ss b1out4 b1out5 b1out6 b1out7 b1out8 v ss b1out9 g2out0 g2out1 g2out2 v ss g2out3 g2out4 g2out5 g2out6 g2out7 v dd v ss g2out8 g2out9 g1out0 g1out1 g1out2 v ss g1out3 g1out4 g1out5 g1out6 o o o o o o o o o o o o o o o o o o o o o o o o o o o power supply gnd blue data output (port 1) blue data output (port 1) blue data output (port 1) blue data output (port 1) gnd blue data output (port 1) blue data output (port 1) blue data output (port 1) blue data output (port 1) blue data output (port 1) gnd blue data output (port 1) green data output (port 2) green data output (port 2) green data output (port 2) gnd green data output (port 2) green data output (port 2) green data output (port 2) green data output (port 2) green data output (port 2) power supply gnd green data output (port 2) green data output (port 2) green data output (port 1) green data output (port 1) green data output (port 1) gnd green data output (port 1) green data output (port 1) green data output (port 1) green data output (port 1) pin no. symbol i/o description input pin processing for open status
7 CXD2467AQ 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 g1out7 v ss g1out8 g1out9 r2out0 r2out1 r2out2 v ss r2out3 r2out4 r2out5 r2out6 r2out7 v dd v ss r2out8 r2out9 r1out0 r1out1 r1out2 r1out3 r1out4 r1out5 r1out6 r1out7 v dd v ss r1out8 r1out9 pcg vb2 vb1 v ss hb dwn o o o o o o o o o o o o o o o o o o o o o o o o o o o o green data output (port 1) gnd green data output (port 1) green data output (port 1) red data output (port 2) red data output (port 2) red data output (port 2) gnd red data output (port 2) red data output (port 2) red data output (port 2) red data output (port 2) red data output (port 2) power supply gnd red data output (port 2) red data output (port 2) red data output (port 1) red data output (port 1) red data output (port 1) red data output (port 1) red data output (port 1) red data output (port 1) red data output (port 1) red data output (port 1) power supply gnd red data output (port 1) red data output (port 1) pcg pulse output vb2 signal output vb1 signal output gnd hb signal output up/down inversion signal output pin no. symbol i/o description input pin processing for open status
8 CXD2467AQ 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 vst vck v dd v ss enb blk hck1 hck2 v dd dck1 dck1x dck2 dck2x hst v ss rgt xrgt frp prg clp1 clp2 sha shb shc shd inv v dd v ss iract oract test1 test2 test3 test4 psave1 o o o o o o o o o o o o o o o o o o o o o o o o i v start pulse output v clock pulse output power supply gnd enb pulse output blk pulse output h clock pulse output 1 h clock pulse output 2 (reversed phase) power supply auxiliary pulse output auxiliary pulse output auxiliary pulse output auxiliary pulse output h start pulse output gnd left/right inversion signal output left/right inversion signal output (reversed polarity) ac drive inversion pulse output prg pulse output pedestal clamp pulse output 1 pedestal clamp pulse output 2 external sample-and-hold driver control signal output external sample-and-hold driver control signal output external sample-and-hold driver control signal output external sample-and-hold driver control signal output external sample-and-hold driver control signal output power supply gnd auxiliary pulse output auxiliary pulse output test pin (connect to gnd.) test pin (connect to gnd.) test pin (connect to v dd .) test pin (connect to v dd .) power saving pin (high: standby status, low: normal status) l pin no. symbol i/o description input pin processing for open status
9 CXD2467AQ 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 psave2 r1in7 r1in6 v dd v ss r1in5 r1in4 r1in3 r1in2 r1in1 r1in0 r2in7 r2in6 r2in5 r2in4 v dd v ss r2in3 r2in2 r2in1 r2in0 g1in7 g1in6 g1in5 g1in4 g1in3 g1in2 v ss g1in1 g1in0 g2in7 g2in6 g2in5 g2in4 g2in3 i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i power saving pin (high: standby status, low: normal status) red data input (port 1) red data input (port 1) power supply gnd red data input (port 1) red data input (port 1) red data input (port 1) red data input (port 1) red data input (port 1) red data input (port 1) red data input (port 2) red data input (port 2) red data input (port 2) red data input (port 2) power supply gnd red data input (port 2) red data input (port 2) red data input (port 2) red data input (port 2) green data input (port 1) green data input (port 1) green data input (port 1) green data input (port 1) green data input (port 1) green data input (port 1) gnd green data input (port 1) green data input (port 1) green data input (port 2) green data input (port 2) green data input (port 2) green data input (port 2) green data input (port 2) l pin no. symbol i/o description input pin processing for open status
10 CXD2467AQ 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 g2in2 g2in1 g2in0 v dd v ss b1in7 b1in6 b1in5 b1in4 b1in3 b1in2 b1in1 b1in0 b2in7 b2in6 b2in5 v ss b2in4 b2in3 b2in2 b2in1 b2in0 r1osd1 r1osd0 g1osd1 g1osd0 b1osd1 b1osd0 v dd v ss ym1 ys1 r2osd1 r2osd0 g2osd1 i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i green data input (port 2) green data input (port 2) green data input (port 2) power supply gnd blue data input (port 1) blue data input (port 1) blue data input (port 1) blue data input (port 1) blue data input (port 1) blue data input (port 1) blue data input (port 1) blue data input (port 1) blue data input (port 2) blue data input (port 2) blue data input (port 2) gnd blue data input (port 2) blue data input (port 2) blue data input (port 2) blue data input (port 2) blue data input (port 2) osd red data input (port 1) osd red data input (port 1) osd green data input (port 1) osd green data input (port 1) osd blue data input (port 1) osd blue data input (port 1) power supply gnd osd ym input (port 1) osd ys input (port 1) osd red data input (port 2) osd red data input (port 2) osd green data input (port 2) l l ? h: pull-up, l: pull-down pin no. symbol i/o description input pin processing for open status
11 CXD2467AQ electrical characteristics dc characteristics (v ss = 0v, topr = 20 to +75 c) item supply voltage input voltage 1 input voltage 2 input voltage 3 output voltage current consumption v dd v ih1 v il1 v ih2 v il2 vc (center level) v ih3 ? 2 v il3 ? 2 v oh v ol i dd symbol applicable pins clk1c, clk2 clk3c, clk4 ? 1 clk1p, clk1n clk3p, clk3n all output pins cmos input cell cmos schmitt trigger input cell small-amplitude differential input clk = 135mhz v dd = 3.3v output load = 30pf ? 3 3.0 0.65v dd v ss 0.8v dd v ss (v dd 0.606) 0.1 v il3 + 0.3 v ss v dd 0.5 v ss 3.3 v dd 0.606 3.6 v dd + 0.3 0.25v dd v dd + 0.3 0.2v dd (v dd 0.606) + 0.1 v dd v ih3 0.3 v dd 0.4 490 360 v ma conditions min. typ. max. unit ? 1 input pins other than those indicated in items input voltage 1 and input voltage 3. ? 2 v ih3 > (maximum vc value) and v il3 < (minimum vc value). ? 3 psave1 = psave2 = h ac characteristics (v dd = 3.3 0.3v, v ss = 0v, topr = 20 to +75 c) ? 4 rgb input, osd input, hdin1, hdin2, vdin item clock input cycle output rise/fall delay time output rise/fall delay time output rise/fall delay time output rise/fall delay time cross-point time difference cross-point time difference tor/tof tor/tof tor/tof tor/tof ? t ? t symbol applicable pins clk1, clk3 clk2, clk4 ? 4 ? 4 hck1, hck2, hst pcg, vst, vck, enb, blk clkout all other output pins hck1, hck2 hck1, hck2 cl = 90pf cl = 50pf cl = 50pf cl = 30pf cl = 90pf cl = 90pf 7.4 14.8 3.5 1.5 9 9 8 9 5 48 12 12 11 12 50 19 19 18 19 5 52 ns conditions min. typ. max. unit tis tih input setup time input hold time
12 CXD2467AQ timing definition clk1p, clk3p clk1n, clk3n clk2, clk4 v ih3 v il3 v ih3 v il3 0v 0v v dd v dd 50% 50% 50% clk1c, clk3c rgb input, osd input hdin1, hdin2, vdin1 50% v dd tih 0v 50% 50% tis clk1p, clk3p clk1n, clk3n clk2, clk4 v ih3 v il3 v ih3 v il3 0v 0v v dd v dd 50% 50% 50% clk1c, clk3c 50% 0v v dd clkout outputs other than clkout outputs other than clkout 0v v dd 0v v dd tor tof 50% 50% 50% 50% 50% 50% 50% tor 50% tof hck1 hck2 hck1, hck2 0v v dd 0v v dd 0v v dd th ? t ? t tl 50% 50% 50% 50% 50% 50% 50%
13 CXD2467AQ parallel transfer data ac characteristics (v dd = 3.3 0.3v, v ss = 0v, topr = 20 to +75 c) item pctl setup time with respect to rise of pclk pctl hold time with respect to rise of pclk pdat[9:0] setup time with respect to rise of pclk pdat[9:0] hold time with respect to rise of pclk pclk pulse width tcs tch tds tdh tw symbol 8t ? 5 8t 4t 4t 4t min. typ. max. ? 5 t: master clock (clk1p/clk1n, clk1c, clk3p/clk3n, clk3c) cycle [ns] timing definition pctl pclk pdat[9:0] tw tds 50% 50% 50% 50% 50% 50% tdh tcs tw tch v dd v dd v dd 0v 0v 0v
14 CXD2467AQ description of operation 1. dsd and tg blocks 1-1. description of input/output pins (a) sync signal input pins (hdin1 and vdin1) horizontal and vertical separate sync signals are input to hdin1 (pin 22) and vdin1 (pin 23), respectively. the CXD2467AQ supports only non-interlace sync signals with a dot clock of 135mhz or less. also, the hsync width should be 40 dot clocks or more, and the vsync width, 1h or more. (b) sync signal polarity setting pins (hdpol1 and vdpol1) the polarity of the input horizontal and vertical sync signals are set by hdpol1 (pin 24) and vdpol1 (pin 25), respectively. set to high level for positive polarity, and to low level for negative polarity. (c) master clock input pins (clk1p/clk1n, clk1c and clk2) and clock selection pins (clksel1 and clksel2) phase comparison is performed by an external circuit and a clock synchronized to the sync signal is input. the 1/n (n is the number of clocks during one horizontal period) frequency-divided dot clock pulse is output from hret (pin 51) for the external phase comparator. the master clock input pins consist of clk1p/clk1n (pins 26 and 27) for small-amplitude differential input (center level: 2.0v, amplitude: 0.4v), and clk1c (pin 29) and clk2 (pin 31) for cmos level input for a total of three channels. these are selected according to clksel1 (pin 35) and clksel2 (pin 36). clksel1 clksel2 selected clock input pins l h l l h clk1p/clk1n (small-amplitude differential input, input at the same frequency as the dot clock) clk1c (cmos level input, input at the same frequency as the dot clock) clk2 (cmos level input, input at 1/2 the frequency of the dot clock) : don't care (d) clock polarity switching pin (clkpol1) when clk1p/1n or clk1c is selected, the clock is 1/2 frequency divided inside the ic using the falling edge of the hd pulse as the reference. the polarity of this 1/2 frequency-divided clock is switched by clkpol1 (pin 37). normally clkpol1 is used at low level. clk1p clkpol1 = l clkpol1 = h hdin1 (active low) internal clock for dsd and tg blocks (e) rgb signal input pins (r1in, r2in, g1in, g2in, b1in and b2in) these pins input rgb signals that have been demultiplexed to 1:2. the red signal is input to r1in (pins 172, 173 and 176 to 181) and r2in (pins 182 to 185 and 188 to 191), the green signal to g1in (pins 192 to 197, 199 and 200) and g2in (pins 201 to 208), and the blue signal to b1in (pins 211 to 218) and b2in (pins 219 to 221 and 223 to 227).
15 CXD2467AQ (f) osd signal input pins (r1osd, r2osd, g1osd, g2osd, b1osd, b2osd, ym1, ym2, ys1 and ys2) these pins input osd signals that have been demultiplexed to 1:2. the red signal is input to r1osd (pins 228 and 229) and r2osd (pins 238 and 239), the green signal to g1osd (pins 230 and 231) and g2osd (pins 1 and 240), and the blue signal to b1osd (pins 232 and 233) and b2osd (pins 2 and 3). in addition, the ym signal is input to ym1 (pin 236) and ym2 (pin 4), and the ys signal to ys1 (pin 237) and ys2 (pin 5). (g) clock output pin (clkout) the internal master clock is output from clkout (pin 33). (h) rgb signal output pins (r1out, r2out, g1out, g2out, b1out and b2out) these pins output the arithmetically processed rgb signals in the 1:2 demultiplexed state. the red signal is output from r1out (pins 118 to 125, 128 and 129) and r2out (pins 105 to 107, 109 to 113, 116 and 117), the green signal from g1out (pins 93 to 95, 97 to 101, 103 and 104) and g2out (pins 80 to 82, 84 to 88, 91 and 92), and the blue signal from b1out (pins 68 to 71, 73 to 77 and 79) and b2out (pins 56 to 65). (i) power saving pins (psave1 and psave2) the gamma block ram can be set to standby mode using both psave1 (pin 170) and psave2 (pin 171). the ram operates normally when these pins are set to low level, and enters standby mode to reduce power consumption when set to high level. at this time data can not be set to or read from the ram. however, data set in advance in the ram is held even in standby mode. in addition, the gamma block ram output is the data held just before the pin voltage changes to high level, so the ram output changes according to the data set in the ram, etc. therefore, using the mute function to fix the CXD2467AQ output to the desired level in standby mode is recommended. 1-2. rgb signal and osd signal pipeline delay the rgb signal i/o pipeline delay is 42 dot clocks. in addition, the osd, ym and ys signal pipeline delay is 12 dot clocks. note that the phase relationship between each clock and the rgb signals is as shown in the figures below. this relationship is the same for the osd, ym and ys signals. (1) clk1p/clk1n and clk1c input (clkpol1 = low) n 2 n 42 n 40 n 38 n 36 n 34 n 32 n 30 n 28 n 26 n 24 n 41 n 39 n 37 n 35 n 33 n 31 n 29 n 27 n 25 n 23 n n + 2 n + 4 n + 6 n + 8 n + 10 n+ 12 n + 14 n + 16 n + 18 hd (active low) clk1p r1in r2in clkout r1out r2out n 1 n + 1 n + 3 n + 5 n + 7 n + 9 n + 11 n + 13 n + 15 n + 17 n + 19 n 44 n 43
16 CXD2467AQ (3) clk2 input n 2 n 42 n 40 n 38 n 36 n 34 n 32 n 30 n 28 n 26 n 24 n 41 n 39 n 37 n 35 n 33 n 31 n 29 n 27 n 25 n 23 n n + 2 n + 4 n + 6 n + 8 n + 10 n+ 12 n + 14 n + 16 n + 18 clk2 r1in r2in clkout r1out r2out n 1 n + 1 n + 3 n + 5 n + 7 n + 9 n + 11 n + 13 n + 15 n + 17 n + 19 n 44 n 43 1-3. description of dsd block signal processing functions the dsd block signal processing flow is shown below. the input rgb signals undergo fine picture quality adjustment in the order of user adjustment, white balance adjustment and gamma correction. further, the CXD2467AQ is also equipped with various adjustment functions such as black frame processing, mute, osd, limiter, and negative/positive inversion. user bright user gain user adjustment block black frame processing block mute block osd block limiter block negative/positive inversion block sub bright sub gain white balance adjustment block black frame mute gam bright gam gain gamma correction block invert select limit gamma r, g, b in r, g, b osd ys, ym r, g, b out osd (2) clk1p/clk1n and clk1c input (clkpol1 = high) n 2 n 44 n 40 n 38 n 36 n 34 n 32 n 30 n 28 n 26 n 24 n 43 n 39 n 37 n 35 n 33 n 31 n 29 n 27 n 25 n 23 n n + 2 n + 4 n + 6 n + 8 n + 10 n+ 12 n + 14 n + 16 n + 18 hd (active low) clk1p r1in r2in clkout r1out r2out n 1 n + 1 n + 3 n + 5 n + 7 n + 9 n + 11 n + 13 n + 15 n + 17 n + 19 n 42 n 41
17 CXD2467AQ the various signal processing functions are described below. note that the coefficients used for each arithmetic operation are set through the parallel i/f block. see the individual descriptions of each parallel i/f block item for a detailed description of the parallel i/f block. (a) user gain block this block performs multiplication processing as the user gain adjustment. multiplication is performed as follows using the 8-bit data a[7:0] input to this ic and an 8-bit coefficient b[7:0]. c[15:0] = a[7:0] b[7:0] the upper 12 bits c[15:4] of the arithmetic results are output. next, the c[4] value is checked and rounding is performed to 11 bits. further, the msb of the rounded 11 bits is checked, clipping is performed to prevent overflow, and the lower 10 bits are output. note that since the coefficient has 8 bits and the 5th bit of the arithmetic results is rounded, the maximum gain by this operation is 255/32 = 7.96875 times and this can be varied in 256 steps. the arithmetic coefficient is shared by r, g and b, and the initial value is 020h. input a[7:0] coefficient b[7:0] c[15:4] output a b rounding and clipping 8 8 12 10 (b) user bright block this block performs addition and subtraction processing as the user bright adjustment. the 10 bits of data a[9:0] output from the user gain block, a 10-bit coefficient b[9:0], and a 1-bit code are used as the inputs to perform arithmetic processing with an accuracy of 1 bit. addition is performed when the code = 0, and subtraction when the code = 1. however, when performing subtraction, set an arithmetic coefficient that is the twos complement of the number to be subtracted. the initial adder performs the following addition: c[10:0] = a[9:0] + b[9:0] then, overflow and underflow are judged according to c[10] which is the msb of the arithmetic results and the code data value. 3ffh is output when overflow occurs, and 000h when underflow occurs. note that the arithmetic coefficient and code are shared by r, g and b, and the initial values are 000h and 0h, respectively. input a[9:0] coefficient b[9:0] c[10:0] output a + b clipping 10 10 code 11 10
18 CXD2467AQ (d) sub bright block this block performs addition and subtraction processing as the white balance bright adjustment. note that the block configuration is the same as the user bright block. however, the arithmetic coefficients and codes can be set independently for r, g and b, and the initial values are 000h and 0h for each, respectively. (e) gamma block this block performs gamma correction for the user- and white balance-adjusted signal. this block comprises a 10-bit 1024-word ram, and the gamma correction curve can be set as desired. the results of this correction are output as 10 bits. the ram data is set through the parallel i/f block. note that the ram output is undetermined while data is being set in this ram, and also during power-on. input output 10 10 ram 10bit 1024 word (f) gamma gain block this block performs multiplication processing for the gamma-corrected signal as the gain adjustment for correcting variance in the vt curve of the lcd panel. multiplication is performed as follows using the 10-bit data a[9:0] output from the gamma block and an 8-bit coefficient b[7:0] as inputs. c[17:0] = a[9:0] b[7:0] the upper 12 bits c[17:6] of the arithmetic results are output. next, the c[6] value is checked and rounding is performed to 11 bits. further, the msb of the rounded 11 bits is checked, clipping is performed to prevent overflow, and the lower 10 bits are output. note that since the coefficient has 8 bits and the 7th bit of the arithmetic results is rounded, the maximum gain by this operation is 255/128 = 1.9921875 times and this can be varied in 256 steps. the arithmetic coefficients can be set independently for r, g and b, and the initial value is 080h for each. (c) sub gain block this block performs multiplication processing as the white balance gain adjustment. multiplication is performed as follows using the 10-bit data a[9:0] output from the user bright block and an 8-bit coefficient b[7:0] as inputs. c[17:0] = a[9:0] b[7:0] the upper 13 bits c[17:5] of the arithmetic results are output. next, the c[5] value is checked and rounding is performed to 12 bits. further, the upper 2 bits of the rounded 12 bits are checked, clipping is performed to prevent overflow, and the lower 10 bits are output. note that since the coefficient has 8 bits and the 6th bit of the arithmetic results is rounded, the maximum gain by this operation is 255/64 = 3.984375 times and this can be varied in 256 steps. the arithmetic coefficients can be set independently for r, g and b, and the initial value is 040h for each. input a[9:0] coefficient b[7:0] c[17:5] output a b rounding and clipping 10 8 13 10
19 CXD2467AQ input a[9:0] coefficient b[7:0] c[17:6] output a b rounding and clipping 10 8 12 10 (g) gamma bright block this block performs addition and subtraction processing for the gamma-corrected signal as the bright adjustment for correcting variance in the vt curve of the lcd panel. note that the block configuration is the same as the user bright block. however, the arithmetic coefficients and codes can be set independently for r, g and b, and the initial values are 000h and 0h for each, respectively. (h) black frame block this block can perform processing to fix the blanking period of the video signal to the desired level regardless of the front-end signal processing results. this is effective when attempting to display a video signal which has been pixel-converted using a scan converter, etc., on a lcd panel or other display with a fixed number of pixels. if the number of pixels calculated from the effective period of the video signal to be displayed is less than the number of pixels of the display on which the signal is to be displayed, the blanking period of the video signal is displayed in the excess pixels. at this time, the displayed blanking period can be fixed to the desired level regardless of the gain and bright adjustment, gamma correction or other picture quality adjustment results by processing with this block. here, the desired range of the video signal is replaced with 10-bit data (frm) by switching the video signal (port 1 and port 2) and the coefficients using the pulse output from the pulse decoder. this range can be set as desired by the 11-bit coefficients (h1f, h2f, v1f and v2f) set in the pulse decoder. then separate pulses are output from the pulse decoder for each of the port 1 (r1, g1 and b1) and port 2 (r2, g2 and b2) processing system blocks. by doing so, the black frame display range can be controlled in 1-dot units for the horizontal direction and in 1-line units for the vertical direction. note that the 1-dot unit for the horizontal direction is the 1- dot unit when viewed with the video signal displayed. also, all coefficients are shared by r, g and b, and the initial value is 000h for each. however, note that when all black frame display range coefficients (h1f, h2f, v1f and v2f) are 000h, black frame display processing is not performed regardless of the black frame signal level coefficient values. internal vd output (port 1) horizontal direction display range (h1f) selector selector 10 11 horizontal direction display range (h2f) 11 vertical direction display range (v1f) 11 vertical direction display range (v2f) 11 pulse decoder internal hd internal mclk input (port 1) 10 output (port 2) 10 10 coefficient (frm) 10 input (port 2)
20 CXD2467AQ (j) osd block this block performs video signal half-tone processing and osd-mix processing by inputting the 2-bit osd data for each color and the ys and ym signals. in the initial shift block, the input data is shifted by one bit to the lsb side when the ym signal is high level. for example, when 0f0h is input, 078h is output. video signal half-tone processing is performed in this manner by halving the input data level. the selector-1 block determines the osd level by assigning four types of coefficients with respect to the osd input data. in the red block, r0d is selected and output when the osd data is 0h, r1d when 1h, r2d when 2h, and r3d when 3h. similarly, one of g0d, g1d, g2d or g3d is selected in the green block, and one of b0d, b1d, b2d or b3d in the blue block. next, the selector-2 block performs osd-mix processing by switching the video signal and the data selected by the selector-1 block using the ys signal. here, the selector-1 block output data is selected and osd-mix processing is performed when the ys signal is high level. the four coefficients can be set independently for r, g and b, and the initial values are all 000h. these coefficients are all 10 bits, and the osd data is 2 bits for each of r, g and b, so 4 half tones can be selected as desired from among 1024 half tones for each of r, g and b. therefore, the desired 64 (= 2 6 ) colors can be selected from among the total 1.07374 billion (= 2 30 ) colors for r, g and b. selector-2 shift ys signal 10 output 10 10 10 10 coefficient (r0d) coefficient (r1d) coefficient (r2d) coefficient (r3d) 2 osd data 10 10 10 ym signal input selector-1 (i) mute block this block performs mute processing by replacing the video signal with data of the desired level. of the arithmetic coefficients set from the register, the mute data can be set independently for r, g and b, and the initial value is 000h for each. also, the mute processing select data is shared by r, g and b, and the initial value is 1h. therefore, mute is applied in the initial status. this is because the gamma block ram output value is undetermined in the initial status. therefore, note that in order to output the video signal, the mute processing select data must be set to 0h after data is set in the ram. select data output selector 10 input 10 10 coefficient (mute level)
21 CXD2467AQ (k) limiter block this block performs limiter processing so that the output signal does not exceed a certain range. first, the input data is compared with the low-side limiter level llim and high-side limiter level hlim coefficients. when these results are input data llim, the output is clipped at the llim level. when hlim input data, the output is clipped at the hlim level. when llim < in < hlim, the input data is output directly. note that the two coefficients are shared by r, g and b, and the initial values are both 000h. set the two coefficients so as to constantly maintain the relationship llim < hlim. also, when both coefficient values are 000h, limiter processing is not performed. output limiter 10 input 10 10 coefficient (hlim) 10 coefficient (llim) (l) negative/positive inversion this block performs negative/positive inversion processing. here, negative/positive inversion processing is performed by outputting the input data directly when the select data is low, or inverting and outputting the input data when the select data is high. the select data is shared by r, g and b, and the initial value is 0h. select data output selector 10 input 10
22 CXD2467AQ 2. iract block the iract block consists of frequency divider and pulse generation circuits, and outputs a pulse synchronized with the horizontal sync signal input to hdin2 from iract (pin 164). the structure of this block is independent from other blocks in the CXD2467AQ. the clock system is also independent, so the iract block can be operated using a different clock than the tg and dsd blocks. (a) sync signal input pin and signal polarity switching pin (hdin2 and hdpol2) the horizontal sync signal for the iract block is input to hdin2 (pin 38), and the sync signal polarity is set by hdpol2 (pin 39). set hdpol2 to high level when the horizontal sync signal is positive polarity, and to low level when negative polarity. (b) clock input pins (clk3p/clk3n, clk3c and clk4) and clock selection pins (clksel3 and clksel4) these are the clock input pins for the iract block. like the master clock, a clock synchronized to the horizontal sync signal is input. the 1/n (n is the number of clocks during one horizontal period) frequency- divided clock pulse is output from irret (pin 50). like the master clock, the clock input pins consist of clk3p/clk3n (pins 40 and 41) for small-amplitude differential input (center level: 2.0v, amplitude: 0.4v), and clk3c (pin 44) and clk4 (pin 46) for cmos level input for a total of three channels. these are selected according to clksel3 (pin 47) and clksel4 (pin 48). clksel3 clksel4 selected clock input pins l h l l h clk3p/clk3n (small-amplitude differential input, input at the same frequency as the dot clock) clk3c (cmos level input, input at the same frequency as the dot clock) clk4 (cmos level input, input at 1/2 the frequency of the dot clock) (c) clock polarity switching pin (clkpol2) when clk3p/3n or clk3c is selected, the clock is 1/2 frequency divided inside the ic using the falling edge of the hd pulse as the reference. the polarity of this 1/2 frequency-divided clock is switched by clkpol2 (pin 49). normally clkpol2 is used at low level. hdin2 (active low) clk3p clkpol2 = l internal clock for iract block clkpol2 = 2 : don't care
23 CXD2467AQ 3. system clear pin (xclr) all internal circuits are initialized by setting xclr (pin 53) low. initialization should be performed during power- on. 4. parallel i/f block register data settings in this ic are performed by parallel data. as shown in the timing chart below, the parallel i/f comprises a total 12-bit wide bus consisting of control signal pctl (pin 8), clock signal pclk (pin 9) and 10-bit wide data signal pdat[9:0] (pins 10 to 17, 20 and 21). the data signal is input in the order of main address, sub address and data. when setting data in this ic, divide the data into five blocks as shown in the table below. next, the sub address specifies the initial address of the data to be written in the block designated by the main address. the data is set sequentially from the data at the address designated by the sub address. the address of each data set thereafter is automatically incremented by +1 from the address designated by the sub address, so further address setting is unnecessary. this makes it possible to set only the necessary data from the desired address of the desired block. timing chart pclk (pin 9) pdat[9:0] (pins 10 to 17, 20 and 21) pctl (pin 8) data main address sub address main address table main address set block 000h 001h 002h 003h 004h gamma block (red) ram gamma block (green) ram gamma block (blue) ram dsd arithmetic coefficients for other than gamma block tg and iract block setting data 4-1. gamma block (main address: 000h to 002h) in this block, the gamma correction data is set in a 10-bit 1024-word ram. here, the set sub address directly becomes the ram write address. thereafter, the ram write address is automatically incremented by +1. following the main address, designate the ram write start address in the sub address with 10 bits, then set the gamma correction data in 10 bits.
24 CXD2467AQ 4-2. dsd block (main address: 003h) the dsd block data format is as follows. data format sub address 000h 001h 002h 003h 004h 005h 006h 007h 008h 009h 00ah 00bh 00ch 00dh 00eh 00fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01ah 01bh 01ch 01dh 01eh 01fh 020h 021h 022h 023h 024h 025h 026h 027h data pdat9 pdat8 pdat7 pdat6 pdat5 pdat4 pdat3 pdat2 pdat1 pdat0 ub9 rsb9 gsb9 bsb9 rgb9 ggb9 bgb9 frm9 h1f9 h2f9 v1f9 v2f9 rm9 gm9 bm9 r0d9 r1d9 r2d9 r3d9 g0d9 g1d9 g2d9 g3d9 b0d9 b1d9 b2d9 b3d9 llim9 hlim9 ubf ub8 rsbf rsb8 gsbf gsb8 bsbf bsb8 rgbf rgb8 ggbf ggb8 bgbf bgb8 frm8 h1f8 h2f8 v1f8 v2f8 rm8 gm8 bm8 r0d8 r1d8 r2d8 r3d8 g0d8 g1d8 g2d8 g3d8 b0d8 b1d8 b2d8 b3d8 llim8 hlim8 ug7 ub7 rsg7 rsb7 gsg7 gsb7 bsg7 bsb7 rgg7 rgb7 ggg7 ggb7 bgg7 bgb7 frm7 h1f7 h2f7 v1f7 v2f7 rm7 gm7 bm7 r0d7 r1d7 r2d7 r3d7 g0d7 g1d7 g2d7 g3d7 b0d7 b1d7 b2d7 b3d7 llim7 hlim7 ug6 ub6 rsg6 rsb6 gsg6 gsb6 bsg6 bsb6 rgg6 rgb6 ggg6 ggb6 bgg6 bgb6 frm6 h1f6 h2f6 v1f6 v2f6 rm6 gm6 bm6 r0d6 r1d6 r2d6 r3d6 g0d6 g1d6 g2d6 g3d6 b0d6 b1d6 b2d6 b3d6 llim6 hlim6 ug5 ub5 rsg5 rsb5 gsg5 gsb5 bsg5 bsb5 rgg5 rgb5 ggg5 ggb5 bgg5 bgb5 frm5 h1f5 h2f5 v1f5 v2f5 rm5 gm5 bm5 r0d5 r1d5 r2d5 r3d5 g0d5 g1d5 g2d5 g3d5 b0d5 b1d5 b2d5 b3d5 llim5 hlim5 ug4 ub4 rsg4 rsb4 gsg4 gsb4 bsg4 bsb4 rgg4 rgb4 ggg4 ggb4 bgg4 bgb4 frm4 h1f4 h2f4 v1f4 v2f4 rm4 gm4 bm4 r0d4 r1d4 r2d4 r3d4 g0d4 g1d4 g2d4 g3d4 b0d4 b1d4 b2d4 b3d4 llim4 hlim4 ug3 ub3 rsg3 rsb3 gsg3 gsb3 bsg3 bsb3 rgg3 rgb3 ggg3 ggb3 bgg3 bgb3 frm3 h1f3 h2f3 v1f3 v2f3 rm3 gm3 bm3 r0d3 r1d3 r2d3 r3d3 g0d3 g1d3 g2d3 g3d3 b0d3 b1d3 b2d3 b3d3 llim3 hlim3 ug2 ub2 rsg2 rsb2 gsg2 gsb2 bsg2 bsb2 rgg2 rgb2 ggg2 ggb2 bgg2 bgb2 frm2 h1f2 h2f2 v1f2 v2f2 smsel rm2 gm2 bm2 r0d2 r1d2 r2d2 r3d2 g0d2 g1d2 g2d2 g3d2 b0d2 b1d2 b2d2 b3d2 llim2 hlim2 ug1 ub1 rsg1 rsb1 gsg1 gsb1 bsg1 bsb1 rgg1 rgb1 ggg1 ggb1 bgg1 bgb1 frm1 h1f1 h2f1 v1f1 v2f1 invsel rm1 gm1 bm1 r0d1 r1d1 r2d1 r3d1 g0d1 g1d1 g2d1 g3d1 b0d1 b1d1 b2d1 b3d1 llim1 hlim1 ug0 ub0 rsg0 rsb0 gsg0 gsb0 bsg0 bsb0 rgg0 rgb0 ggg0 ggb0 bgg0 bgb0 frm0 h1f0 h1f10 h2f0 h2f10 v1f0 v1f10 v2f0 v2f10 rm0 gm0 bm0 r0d0 r1d0 r2d0 r3d0 g0d0 g1d0 g2d0 g3d0 b0d0 b1d0 b2d0 b3d0 llim0 hlim0 020h 000h 040h 000h 040h 000h 040h 000h 080h 000h 080h 000h 080h 000h 000h 000h 000h 000h 000h 000h 000h 000h 004h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h initial value : don't care
25 CXD2467AQ the detailed setting contents are described below. (a) ug: user gain block coefficient setting the user gain block arithmetic coefficient is set in ug7 (msb) to ug0 (lsb). the initial value is 20h. (b) ub and ubf: user bright block coefficient settings the user bright block arithmetic coefficient is set in ub9 (msb) to ub0 (lsb), and the code bit is set in ubf. addition is performed when the code bit = 0, and subtraction when the code bit = 1. when performing subtraction, set an arithmetic coefficient that is the twos complement of the number to be subtracted. the initial values of the arithmetic coefficient and the code bit are 000h and 0h, respectively. (c) rsg, gsg and bsg: sub gain block coefficient settings the r, g and b sub gain block arithmetic coefficients are set in rsg7 (msb) to rsg0 (lsb), gsg7 (msb) to gsg0 (lsb) and bsg7 (msb) to bsg0 (lsb), respectively. the initial value of each coefficient is 40h. (d) rsb, rsbf, gsb, gsbf, bsb and bsbf: sub bright block coefficient settings the r, g and b sub bright block arithmetic coefficients are set in rsb9 (msb) to rsb0 (lsb), gsb9 (msb) to gsb0 (lsb) and bsb9 (msb) to bsb0 (lsb), respectively. also, the r, g and b code bits are set in rsbf, gsbf and bsbf, respectively. addition is performed when the code bit = 0, and subtraction when the code bit = 1. when performing subtraction, set an arithmetic coefficient that is the twos complement of the number to be subtracted. the initial values of the arithmetic coefficients and the code bits are 000h and 0h, respectively. (e) rgg, ggg and bgg: gamma gain block coefficient settings the r, g and b gamma gain block arithmetic coefficients are set in rgg7 (msb) to rgg0 (lsb), ggg7 (msb) to ggg0 (lsb) and bgg7 (msb) to bgg0 (lsb), respectively. the initial value of each coefficient is 80h. (f) rgb, rgbf, ggb, ggbf, bgb and bgbf: gamma bright block coefficient settings the r, g and b gamma bright block arithmetic coefficients are set in rgb9 (msb) to rgb0 (lsb), ggb9 (msb) to ggb0 (lsb) and bgb9 (msb) to bgb0 (lsb), respectively. also, the r, g and b code bits are set in rgbf, ggbf and bgbf, respectively. addition is performed when the code bit = 0, and subtraction when the code bit = 1. when performing subtraction, set an arithmetic coefficient that is the twos complement of the number to be subtracted. the initial values of the arithmetic coefficients and the code bits are 000h and 0h, respectively. (g) frm, h1f, h2f, v1f and v2f: black frame processing block coefficient settings the black frame signal level for the black frame processing block is set in frm9 (msb) to frm0 (lsb). in addition, the black frame display range coefficients for the horizontal direction are set in h1f10 (msb) to h1f0 (lsb) and h2f10 (msb) to h2f0 (lsb), and for the vertical direction in v1f10 (msb) to v1f0 (lsb) and v2f10 (msb) to v2f0 (lsb). the horizontal direction display range can be set in 1-dot units using the hd input edge as the reference. the falling edge is used as the reference when hd input is negative polarity input, and the rising edge when positive polarity input. the vertical direction display range can be set in 1-line units using the vd input edge as the reference. the falling edge is used as the reference when vd input is negative polarity input, and the rising edge when positive polarity input. set the display range values in h1f , h2f, v1f and v2f. note that when all black frame display range coefficients are 000h, black frame processing is not performed. the initial value of each coefficient is 000h.
26 CXD2467AQ hd (active low) vd (active low) h1f h2f black frame display range black frame display range v1f v2f black frame display range black frame display range (h) smsel, rm, gm and bm: mute block coefficient settings the mute processing select data for the r, g and b mute blocks is set in smsel. also, the r, g and b mute level coefficients are set in rm9 (msb) to rm0 (lsb), gm9 (msb) to gm0 (lsb) and bm9 (msb) to bm0 (lsb), respectively. mute processing is performed when smsel = 1, and not when smsel = 0. the initial values of the select data and mute level coefficients are 1h and 000h, respectively. (i) r0d, r1d, r2d, r3d, g0d, g1d, g2d, g3d, b0d, b1d, b2d and b3d: osd block coefficient settings the r, g and b osd block decoding data is set in r0d9 (msb) to r0d0 (lsb), r1d9 (msb) to r1d0 (lsb), r2d9 (msb) to r2d0 (lsb), r3d9 (msb) to r3d0 (lsb), g0d9 (msb) to g0d0 (lsb), g1d9 (msb) to g1d0 (lsb), g2d9 (msb) to g2d0 (lsb), g3d9 (msb) to g3d0 (lsb), b0d9 (msb) to b0d0 (lsb), b1d9 (msb) to b1d0 (lsb), b2d9 (msb) to b2d0 (lsb) and b3d9 (msb) to b3d0 (lsb). the desired osd color can be set by assigning the decoding data with respect to the input osd data in the osd block. the initial values are all 000h. (j) llim, hlim: limiter block coefficient settings the limiter block limit value data is set in llim9 (msb) to llim0 (lsb) and hlim9 (msb) to hlim0 (lsb). be sure to set data so that the relationship llim < hlim is constantly maintained. note that when 000h is set for both llim and hlim, limiter processing is not performed. the initial values are both 000h. (k) invsel: negative/positive inversion block coefficient setting the negative/positive inversion block select data is set in invsel. negative/positive inversion processing is performed when invsel = 1, and not when invsel = 0. the initial value is 0h, respectively.
27 CXD2467AQ 4-3. tg and iract blocks (main address: 004h) the timing pulses output from the CXD2467AQ are generated according to the data set in the data register. the related registers are shown below. sub addresses 000h to 025h are the tg block related data, and 026h to 02bh are the iract block related data. the tg and iract block data format is as follows. data format sub address 000h 001h 002h 003h 004h 005h 006h 007h 008h 009h 00ah 00bh 00ch 00dh 00eh 00fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01ah 01bh 01ch 01dh 01eh 01fh 020h 021h 022h 023h 024h 025h 026h 027h 028h 029h 02ah 02bh data pdat9 pdat8 pdat7 pdat6 pdat5 pdat4 pdat3 pdat2 pdat1 pdat0 plp9 oru9 ord9 hp9 pcgu9 pcgd9 prgu9 prgd9 enbu9 enbd9 cp1u9 cp1d9 cp2u9 cp2d9 hstu9 hstd9 vcrv9 vp9 fri9 irp9 iru9 ird9 plp8 slvrs oru8 ord8 hp8 pcgu8 pcgd8 prgu8 prgd8 enbu8 enbd8 cp1u8 cp1d8 cp2u8 cp2d8 hstu8 hstd8 vcrv8 vp8 fri8 slds irp8 iru8 ird8 plp7 slprs3 oru7 ord7 hp7 pcgu7 pcgd7 prgu7 prgd7 enbu7 enbd7 cp1u7 cp1d7 cp2u7 cp2d7 hstu7 hstd7 vcrv7 vp7 fri7 mbk1 irp7 iru7 ird7 plp6 slprs2 oru6 ord6 hp6 pcgu6 pcgd6 prgu6 prgd6 enbu6 enbd6 cp1u6 cp1d6 cp2u6 cp2d6 hstu6 hstd6 vcrv6 vp6 slfr fri6 mbk0 irp6 iru6 ird6 plp5 slprs1 oru5 ord5 hp5 pcgu5 pcgd5 prgu5 prgd5 enbu5 enbd5 cp1u5 cp1d5 cp2u5 cp2d5 hstu5 hstd5 vcrv5 vp5 hscn fri5 shp0 irp5 iru5 ird5 plp4 slprs0 oru4 ord4 hp4 pcgu4 pcgd4 prgu4 prgd4 enbu4 enbd4 cp1u4 cp1d4 cp2u4 cp2d4 hstu4 hstd4 vcrv4 vp4 vscn fri4 shp1 irp4 iru4 ird4 plp3 slhck1 oru3 ord3 hp3 pcgu3 pcgd3 prgu3 prgd3 enbu3 enbd3 cp1u3 cp1d3 cp2u3 cp2d3 hstu3 hstd3 vcrv3 vp3 hb fri3 shp2 irp3 iru3 ird3 plp2 slhck0 oru2 ord2 hp2 pcgu2 pcgd2 prgu2 prgd2 enbu2 enbd2 cp1u2 cp1d2 cp2u2 cp2d2 hstu2 hstd2 vcrv2 vp2 vb1 fri2 shp3 irp2 slhr iru2 ird2 plp1 plp11 oru1 oru11 ord1 ord11 hp1 hp11 pcgu1 pcgu11 pcgd1 pcgd11 prgu1 prgu11 prgd1 prgd11 enbu1 enbu11 enbd1 enbd11 cp1u1 cp1u11 cp1d1 cp1d11 cp2u1 cp2u11 cp2d1 cp2d11 hstu1 hstu11 hstd1 hstd11 vcrv1 vcrv11 vp1 vb2 fri1 inv irp1 irp11 iru1 iru11 ird1 ird11 plp0 plp10 oru0 oru10 ord0 ord10 hp0 hp10 pcgu0 pcgu10 pcgd0 pcgd10 prgu0 prgu10 prgd0 prgd10 enbu0 enbu10 enbd0 enbd10 cp1u0 cp1u10 cp1d0 cp1d10 cp2u0 cp2u10 cp2d0 cp2d10 hstu0 hstu10 hstd0 hstd10 vcrv0 vcrv10 vp0 vp10 fri0 fri10 irp0 irp10 iru0 iru10 ird0 ird10 297h 015h 080h 000h 000h 000h 022h 000h 086h 000h 142h 000h 086h 000h 100h 000h 0feh 000h 00ch 000h 0c0h 000h 132h 000h 088h 000h 128h 000h 146h 000h 15eh 000h 086h 000h 020h 02eh 3ffh 001h 297h 001h 080h 000h 000h 000h initial value : don't care
28 CXD2467AQ the detailed setting contents are described below. (a) plp: pll counter frequency division ratio setting this sets the frequency division ratio of the 1/n frequency divider (pll counter) for phase comparison. the value of (total number of dots in one horizontal period n) 1 is set in plp11 (msb) to plp0 (lsb). the frequency division ratio can be set up to 4096. however, only even numbers can be set for the value of n. the initial value is 697h (n = 1688). (b) slhck: hck cycle setting the hck1 (pin 142) and hck2 (pin 143) cycle is set in slhck1 (msb) and slhck0 (lsb). 0h is set for lcd panels that perform 6-dot simultaneous sampling, 1h for 12-dot simultaneous sampling, 2h for 18-dot simultaneous sampling and 3h for 24-dot simultaneous sampling. note that hck2 is the reverse-phase signal of hck1. the initial value is 1h (12-dot simultaneous sampling). (c) slprs: pll counter reset cycle setting the pll counter is reset according to the value set in plp, but reset can also be applied separately by hsync. the hsync cycle at which reset is applied is set in slprs3 (msb) to slprs0 (lsb). when 0h is set, the pll counter is not reset. when 1h is set, the front edge of hsync is detected and the pll counter is reset each time hsync is input. the reset cycle increases thereafter so that when fh is set, the pll counter is reset by hsync every 15h. the initial value is 1h (reset every 1h). (d) slvrs: pll counter vsync reset this sets whether to reset the pll counter with each vsync. the pll counter is not reset when set to 0h, and reset when 1h. however, when slprs = 0h (no reset by hsync), the pll counter is not reset regardless of the slvrs setting. the initial value is 0h (no reset). (e) oru/ord: oract pulse settings the oract (pin 165) pulse rise position within one horizontal period is set in oru11 (msb) to oru0 (lsb), and the fall position is set in ord11 (msb) to ord0 (lsb). the pll counter reset timing is used as the reference (all 0). also, the least significant bit is ignored, so setting is in 2-dot units. the initial values are oru = 080h and ord = 000h. (f) hp: picture horizontal position setting the timing at which the counter is initialized to generate the pcg (pin 130), prg (pin 154), enb (pin 140), clp1 (pin 155), clp2 (pin 156), hst (pin 149), hck1 and hck2 horizontal drive pulses within one horizontal period is set in hp11 (msb) to hp0 (lsb). changing this setting causes the phase relationships of the horizontal drive pulses as well as the changing positions of vck (pin 137) and frp (pin 153) relative to hsync to change in an interlocked manner, making it possible to change the picture horizontal position. settings can be made in 1-dot units. note that hck1 and hck2 are initialized at this timing, and change at the cycle set by slhck. (see the timing chart.) the initial value is 022h. (g) pcgu/pcgd, prgu/prgd, enbu/enbd, cp1u/cp1d, cp2u/cp2d and hstu/hstd: horizontal drive pulse settings these set the rise and fall positions of the pcg, prg, enb, clp1, clp2 and hst pulses within one horizontal period. the horizontal drive pulse initialization timing set by hp is used as the reference. (see the timing chart.) also, the least significant bit is ignored, so setting is in 2-dot units. the initial values are as follows. pcgu = 086h/pcgd = 142h prgu = 086h/prgd = 100h enbu = 0feh/enbd = 00ch cp1u = 0c0h/cp1d = 132h cp2u = 088h/cp2d = 128h hstu = 146h/hstd = 15eh
29 CXD2467AQ (h) vcrv: vck pulse polarity inversion position setting the vck and frp pulse polarity inversion position within one horizontal period is set in vcrv11 (msb) to vcrv0 (lsb). the reference is the same as that for the horizontal drive pulse setting above. also, the least significant bit is ignored, so setting is in 2-dot units. the initial value is 086h. (i) vp: picture vertical position setting the picture vertical position is set in vp10 (msb) to vp0 (lsb). changing this setting causes the phase relationships of the vst (pin 136), vck and frp pulses relative to vsync to change in an interlocked manner. settings can be made in 1-line units. the initial value is 020h. (j) hb, vb1 and vb2: lcd panel control signal settings these set the lcd panel control signals. the data set in hb, vb1 and vb2 is output from the hb (pin 134), vb1 (pin 132) and vb2 (pin 131) output pins, respectively. also, when either vb1 or vb2 is set to 0h, the blk pulse is output. the methods of using these signals differ according to the lcd panel, and some lcd panels may not even have input pins supporting these signals. see the specifications of the used lcd panel for details. the initial values are hb = 1h, vb1 = 1h and vb2 = 1h. (k) hscn and vscn: lcd panel scan direction settings these set the horizontal and vertical scan directions of the lcd panel. the hscn setting data is output from rgt (pin 151), and the vscn setting data from dwn (pin 135). also, changing the hscn setting reverses the hck1 and hck2 phases. see the specifications of the used lcd panel for a detailed description of the scan direction. the initial values are hscn = 1h and vscn = 0h. (l) slfr: frp pulse inversion cycle setting this sets the inversion cycle of the polarity inversion pulse (frp pulse) used for ac driving of lcd panels. the polarity is inverted at 1-line cycles when set to 0h, and at 1-field cycles when set to 1h. the initial value is 0h (1-line inversion). (m) shp0, shp1, shp2, shp3 and inv: cxa2112r sample-and-hold control these control the sample-and-hold position of the cxa2112r (sample-and-hold driver). the shp0, shp1, shp2 and shp3 setting data is reflected to sha, shb, shc and shd (pins 157 to 160) as shown below. also, the inv setting data is output directly from the inv (pin 161) output pin. see the specifications of the cxa2112r for a detailed description of control methods. the initial values are shp0 = 0h, shp1 = 0h, shp2 = 0h, shp3 = 0h and inv = 0h. setting shp3 to shp0 output setting output shpa shpb shpc shpd 0000 0001 0010 0011 0100 0101 0110 0111 l h z z l h z z l h l h l h l h l l l l h h h h l l l l h h h h shp3 to shp0 shpa shpb shpc shpd 1000 1001 1010 1011 1100 1101 1110 1111 l h z z l h z z l h l h l h l h z z z z z z z z l l l l h h h h z: high impedance state
30 CXD2467AQ (n) fri: free-running cycle setting when vsync has not been input for a specified period, a judgment of "no signal" is made to allow ac driving of lcd panels even when there is no signal. in this case, a vertical start pulse and frp pulse are output at a specified cycle (free-running operation). the period until a judgment of "no signal" is made and the vst pulse cycle during free-running operation are set in fri10 (msb) to fri0 (lsb). the initial value is 7ffh (2048h cycle). (o) mbk0 and mbk1: decimation operation settings this sets the decimation operation which decimates the display lines at a specified ratio. this ic has two built- in modes: 2/14-line decimation and 1/4-line decimation. mbk0 turns decimation operation on and off, and mbk1 selects the mode. decimation is not performed when mbk0 = 0h, and is performed when mbk0 = 1h. also, 2/14-line decimation is performed when mbk1 = 0h, and 1/4-line decimation when mbk1 = 1h. the initial values are mbk0 = 0h and mbk1 = 0h (no decimation). (p) slds: test data this is test data. set to 0h. the initial value is 0h. (q) irp: iract block frequency divider frequency division ratio setting like the pll counter, this sets the frequency division ratio of the 1/n frequency divider for phase comparison. the value of (total number of dots in one horizontal period n) 1 is set in irp11 (msb) to irp0 (lsb). the frequency division ratio can be set up to 4096. however, only even numbers can be set for the value of n. the initial value is 697h (n = 1688). (r) slhr: iract block frequency divider reset setting this sets whether the iract block frequency divider is reset by the hsync input to hdin2. the frequency divider is reset when 0h, and not reset when 1h. the initial value is 0h (reset). (s) iru/ird: iract pulse settings the iract pulse rise position within one horizontal period is set in iru11 (msb) to iru0 (lsb), and the fall position in ird11 (msb) to ird0 (lsb) relative to the hsync input to hdin2. the iract block frequency divider reset timing is used as the reference (all 0). also, the least significant bit is ignored, so setting is in 2- dot units. the initial values are iru = 080h and ird = 000h. note) the above setting values may be invalid in certain cases. (for example, settings which exceed the number of clocks in 1h or number of lines in 1v of the input signal, etc.) normal pulses will not be output in these cases, so be sure to refer to the setting examples on the following page when making the settings.
31 CXD2467AQ data register setting examples examples of data register settings for typical lcd panels driven by this ic and input signals are shown below. the optimum settings may differ depending on the actual input signal specifications and differences in video signal processing systems, so be sure to adjust the setting values as necessary. (a) example settings when using the lcx028 input signal: sxga (1280 1024 dots, f h = 64khz, f v = 60hz, dot clock = 108mhz) pll counter h position pcg pulse prg pulse enb pulse clp1 pulse hst pulse vck/frp inversion position v position plp = 697h (n = 1688, same as default value) hp = 000h pcgu = 074h/pcgd = 136h prgu = 074h/prgd = 0f6h enbu = 0f6h/enbd = 008h cp1u = 088h/cp1d = 128h hstu = 146h/hstd = 15eh vcrv = 074h vp = 020h (same as default value) pll counter h position pcg pulse prg pulse enb pulse clp1 pulse hst pulse vck/frp inversion position v position free-running frequency plp = 53fh (n = 1344) hp = 042h pcgu = 050h/pcgd = 0d4h prgu = 050h/prgd = 09eh enbu = 09eh/enbd = 002h cp1u = 024h/cp1d = 0b0h hstu = 0ceh/hstd = 0e6h vcrv = 050h vp = 023h fri = 63fh (1600h) (b) example settings when using the lcx023 or lcx017 input signal: xga (1024 768 dots, f h = 48khz, f v = 60hz, dot clock = 65mhz)
32 CXD2467AQ tg and iract block timing chart horizontal direction timing chart 20-dot clocks (ck) horizontal drive pulse initialization position 34ck 128ck 138ck (hdin1) hret oract clp1 clp2 hst hck1 hck2 enb pcg prg vck frp (hdin2) irret iract ? when hscn = 0 (left/right inversion), the hck1 and hck2 phases are reversed. the 1h and 1v cycle frp polarity is not specified. 242ck 136ck 160ck 194ck 114ck 24ck 188ck 122ck 128ck 4ck 14ck data register setting: default (example for input signal with total number of horizontal dots = 1688)
33 CXD2467AQ vertical direction timing chart (hdin1) (vdin1) hret oract vst vck frp hst enb pcg prg blk (hdin2) irret iract ? the 1h and 1v cycle frp polarity is not specified. data register setting: default (example for input signal with total number of vertical lines = 1066)
34 CXD2467AQ vertical direction timing chart (hdin1) (vdin1) hret oract vst vck frp hst enb pcg prg blk (hdin2) irret iract ? the 1h and 1v cycle frp polarity is not specified. data register setting: vb1 = 0 or vb2 = 0, vp = 01e/h, other settings = default (example for input signal with total number of vertical lines = 1000)
35 CXD2467AQ vertical direction timing chart (hdin1) (vdin1) hret oract vst vck frp hst enb pcg prg blk (hdin2) irret iract ? the 1h and 1v cycle frp polarity is not specified. data register setting: mbk0 = 1, mbk1 = 0, vp = 00a/h, other settings = default (example for input signal with total number of vertical lines = 1250)
36 CXD2467AQ vertical direction timing chart (hdin1) (vdin1) hret oract vst vck frp hst enb pcg prg blk (hdin2) irret iract ? the 1h and 1v cycle frp polarity is not specified. data register setting: mbk0 = 1, mbk1 = 1, vp = 00c/h, other settings = default (example for input signal with total number of vertical lines = 1066)
37 CXD2467AQ application circuit osd input osd input from a/d converter to d/a converter hdin1 clkout parallel data input hdin2 clk3p clk3n clk3c clk4 gnd +3.3v 1 0.1 to d/a converter to lcd panel from a/d converter 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 10 10k vdin1 clk1p clk1n clk1c clk2 +3.3v gnd gnd hdpol1 +3.3v vdpol1 clksel1 clksel2 clkpol1 hdpol2 clksel3 clksel4 clkpol2 10 10 10 0.1 0.1 to d/a converter 0.1 0.1 0.1 47k 47k 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 190 191 192 193 194 195 196 183 182 181 184 185 186 187 188 189 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 g2 osd0 b2osd1 b2osd0 ym2 ys2 v dd v ss pctl pclk pdat9 pdat8 pdat7 pdat6 pdat5 pdat4 pdat3 pdat2 v dd v ss pdat1 pdat0 hdin1 vdin1 hdpol1 vdpol1 clk1p clk1n v ss clk1c v ss clk2 v ss clk3n v dd v ss clk3c v ss clk4 clksel3 clksel4 clkpol2 irret hret v ss xclr v dd v ss b2out0 b2out1 b2out2 b2out3 b2 out4 clkout v ss clksel1 clksel2 clkpol1 hdin2 hdpol2 clk3p 61 62 63 64 65 66 67 68 69 70 71 v ss b1out4 b1out5 b1out6 b1out7 b1out8 v ss b1out9 g2out0 g2out1 g2out2 b2out6 b2out5 b2out7 b2out8 b2out9 v dd v ss b1out0 b1out1 b1out2 b1out3 v ss g2out3 g2out4 g2out5 g2out6 g2out7 v dd v ss g2out8 g2out9 g1out0 g1out1 g1out2 v ss g1out3 g1out4 g1out5 g1out6 g1out7 v ss g1out8 g1out9 r2out0 r2out1 r2out2 v ss r2out3 r2out4 r2out5 r2out6 r2out7 v dd v ss r2out8 r2out9 r1out0 r1out1 r1 out2 111 110 109 108 107 106 105 118 119 120 117 116 115 114 113 112 104 103 102 101 100 230 231 232 233 234 235 236 237 238 239 240 r1osd0 r1osd1 b2in0 b2in1 b2in2 b2in3 b2in4 v ss b2in5 b2in6 b2in7 b1in0 b1in1 b1in2 b1in3 b1in4 b1in5 b1in6 b1in7 v ss v dd g2in0 g2in1 g2in2 g2in3 g2in4 g2in5 g2in6 g2in7 g1in0 g1in1 v ss g1in2 g1in3 g1in4 g1in5 g1in6 g1in7 r2in0 r2in1 r2in2 r2in3 v ss v dd r2in4 r2in5 r2in6 r2in7 r1in0 ys1 ym1 v ss v dd b1osd0 b1osd1 g1osd0 g1osd1 g2osd1 r2osd0 r2osd1 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 135 136 137 138 139 140 134 133 132 131 130 129 127 128 126 125 124 123 122 121 r1in1 r1in2 r1in3 r1in4 r1in5 v ss v dd r1in6 r1in7 psave2 psave1 test4 test3 test2 test1 oract iract v ss v dd inv shd shc shb sha clp2 clp1 prg frp xrgt rgt v ss hst dck2x dck2 dck1x dck1 v dd hck2 hck1 blk enb v ss v dd vck vst dwn hb v ss vb1 vb2 pcg r1out9 r1out8 v ss v dd r1out7 r1out6 r1out5 r1out4 r1out3 application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
38 CXD2467AQ package outline unit: mm sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating copper alloy package structure 0.5 0.08 m 0.10 240pin qfp (plastic) 0? to 8? detail a qfp-240p-l022 qfp240-p-3232 7.6g 180 121 32.0 0.1 34.6 0.2 120 61 181 240 160 0.22 ?0.03 + 0.05 4.1 max 0.40 ?0.15 + 0.10 0.145 ?0.03 + 0.05 a 0.25 0.45 min ?0.75 max sony corporation

▲Up To Search▲

Price & Availability of CXD2467AQ

	To Download CXD2467AQ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .